Geometric collapse engineering: a framework for sub-1·5 nm transistor design via environment-induced quantum state reduction

Abstract The miniaturization of field-effect transistors has reached a critical juncture at the 1.5 nm technology node, where conventional drift-diffusion models fail due to dominant quantum effects. We present a device engineering framework grounded in geometric collapse theory, wherein environmental coupling is harnessed as an active switching mechanism rather than treated as a parasitic effect. By exploiting the inherent structure of quantum state space–the Riemann sphere for two-level systems–we demonstrate that asymmetric environmental coupling can force deterministic wavefunction collapse to a desired pointer state within switching timescales. Our approach provides explicit design rules: (1) environmental coupling rates $kappa_Sandkappa_Dmust differ by at least10¹³s{}^-1, (2) effective mass engineering using III-V materials achieves this condition, and (3) symmetry breaking through gate geometry or material composition yields collapse timestau_collapse < 0.1$ ps. This framework reconciles quantum measurement theory with semiconductor device physics, offering a pathway to extend Moore’s Law beyond the 1.5 nm barrier. We analyze the validity of the geometric flow equation, competition with thermal effects at 300 K, the transition from deterministic to probabilistic regimes, and fundamental limits below 1 nm. A comprehensive NEGF simulation with realistic parameters $$α = 0.5$$ confirms the theoretical predictions, demonstrating a $3.86 times 10⁵improvement inI_on/I_off$ ratio compared to conventional tunneling transport. The comprehensive NEGF simulation results, including key parameters and performance metrics, are summarized in Tables 6-12.