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A Novel Enhanced-Majority-Voter Universal Gate in Quantum Dot Cellular Automata with Energy Dissipation Analysis

DOAJ
Authors: S. Umira, R. Qadri, Z.A. Bangi, M. Tariq Banday, G. Mohiuddin Bhat

Year

2017

Paper ID

18028

Status

Peer-reviewed

Abstract Read

~2 min

Abstract Words

213

Citations

4

Abstract

The Quantum effects instigate to dominate device recital when transistor geometries are abridged. Sometimes, transistors refrain to have the properties that mark them beneficial for computational designs. With the intention of keeping pace with Moore’s Law, diverse assessing elements must be developed. An alternative prototype to transistor-based logic is Quantum dot cellular automata. This technology has an enormous capability to provide ultra-high density and extremely low power dissipation. These features allow us to develop high-speed, small and high performance circuits for computation and integration. Architectures made in quantum dot cellular automata have been designed by exploiting either the inverter and the majority gate or universal gates like And-Or-Inverter, NAND-NOR-Inverter, FNZ and AIN. A new universal logic gate called as Enhanced Majority Voter Gate is presented in this paper which enjoys better performance with respect to previously announced universal gates. Design of several logic utilities via the proposed Enhanced Majority Voter Gate is also demonstrated. The functionality and power analysis of this universal gate is verified by the QCA Designer and QCA Pro simulation tool where a comprehensive comparison with the hitherto stated designs confirms the reliable performance of the proposed designs. The proposed Enhanced Majority Voter Gate helps us in framing various cryptographic and security based circuits in Quantum dot cellular automata.

Why This Paper Matters

  • This paper contributes to the Quantum Simulation research area in the Quantum Articles archive.
  • It adds a 2017 reference point for readers tracking recent quantum research.
  • The Quantum effects instigate to dominate device recital when transistor geometries are abridged.

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