Cryogenic interface state modeling workflow for Ge/SiGe quantum-well devices

Abstract Traps at the semiconductor-oxide interface are considered as a major source of instability in semiconductor quantum devices, yet the quantified study of their cryogenic behavior remains limited. In this work, we introduce a transferrable workflow to model the impact of interface states on these devices. This method combines transport measurement with Schrödinger–Poisson simulation and tunneling analysis, and is potentially compatible to different quantum wells (QWs). By demonstrating this workflow experimentally on a practical Ge/SiGe Hall-bar field-effect transistor device, we successfully reconstruct the gradual filling process of interface states and suggest a crossover in the tunneling-trapping process from trap-assisted-tunneling- to Fowler–Nordheim (F–N)-tunneling-involved transport, which refines the conventional F–N-based picture of interface trapping. Our workflow shows the potential of studying cryogenic interface states on different QWs, as well as provide guidelines for enhancing Ge-based quantum device performance by improving barrier crystalline qualities and reducing dislocation-related trap densities.