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Trapped Ion Quantum Computing

Low-depth Circuit Implementation of Parity Constraints for Quantum Optimization

arXiv
Authors: Josua Unger, Anette Messinger, Benjamin E. Niehoff, Michael Fellner, Wolfgang Lechner

Year

2022

Paper ID

6652

Status

Preprint

Abstract Read

~2 min

Abstract Words

117

Citations

N/A

Abstract

We present a construction for circuits with low gate count and depth, implementing three- and four-body Pauli-Z product operators as they appear in the form of plaquette-shaped constraints in QAOA when using the parity mapping. The circuits can be implemented on any quantum device with nearest-neighbor connectivity on a square-lattice, using only one gate type and one orientation of two-qubit gates at a time. We find an upper bound for the circuit depth which is independent of the system size. The procedure is readily adjustable to hardware-specific restrictions, such as a minimum required spatial distance between simultaneously executed gates, or gates only being simultaneously executable within a subset of all the qubits, for example a single line.

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  • We present a construction for circuits with low gate count and depth, implementing three- and four-body Pauli-Z product operators as they appear in the form of plaquette-shaped...

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References & Citation Signals

[1] DOI https://doi.org/arXiv:2211.11287 [2] arXiv https://arxiv.org/abs/2211.11287 [3] Publisher https://arxiv.org/abs/2211.11287

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