Quick Navigation
Topics
Trapped Ion Quantum Computing
Superconducting Qubits
Quantum Chemistry
Implementation of the XY interaction family with calibration of a single pulse
arXiv
Authors: Deanna M. Abrams, Nicolas Didier, Blake R. Johnson, Marcus P. da Silva, Colm A. Ryan
Year
2019
Paper ID
40019
Status
Preprint
Abstract Read
~2 min
Abstract Words
208
Citations
N/A
Abstract
Near-term applications of quantum information processors will rely on optimized circuit implementations to minimize gate depth and therefore mitigate the impact of gate errors in noisy intermediate-scale quantum (NISQ) computers. More expressive gate sets can significantly reduce the gate depth of generic circuits. Similarly, structured algorithms can benefit from a gate set that more directly matches the symmetries of the problem. The XY interaction generates a family of gates that provides expressiveness well tailored to quantum chemistry as well as to combinatorial optimization problems, while also offering reductions in circuit depth for more generic circuits. Here we implement the full family of XY entangling gates in a transmon-based superconducting qubit architecture. We use a composite pulse scheme that requires calibration of only a single gate pulse and maintains constant gate time for all members of the family. This allows us to maintain a high fidelity implementation of the gate across all entangling angles. The average fidelity of gates sampled from this family ranges from 95.67 pm 0.60\% to 99.01 pm 0.15\%, with a median fidelity of 97.35 pm 0.17\%, which approaches the coherence-limited gate fidelity of the qubit pair. We furthermore demonstrate the utility of XY in a quantum approximation optimization algorithm in enabling circuit depth reductions as compared to the CZ only case.
Why This Paper Matters
- This paper contributes to the Quantum Chemistry research area in the Quantum Articles archive.
- It adds a 2019 reference point for readers tracking recent quantum research.
- Near-term applications of quantum information processors will rely on optimized circuit implementations to minimize gate depth and therefore mitigate the impact of gate errors...
Paper Tools
Become a member to use research tools
Sign in to open papers, visit source links, share, cite, compare, copy DOI links, request category corrections, and build your reading list.
Show Paper arXiv Publisher Share
Cite This Paper
Copy URL
Compare
Copy DOI Add to Reading List
Category Correction Request
Category Correction Request
Help us improve classification quality by proposing a better category. Every request is reviewed by an admin.
Sign in to submit a category correction request for this paper.
Log In to SubmitReferences & Citation Signals
Community Reactions
Quick sentiment from readers on this paper.
Score:
0
Likes: 0
Dislikes: 0
Sign in to react to this paper.
Discussion & Reviews (Moderated)
Average Rating: 0.0 / 5 (0 ratings)
No written reviews yet.