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Trapped Ion Quantum Computing
Industrially fabricated single-electron quantum dots in Si/Si-Ge heterostructures
arXiv
Authors: Till Huckemann, Pascal Muster, Wolfram Langheinrich, Varvara Brackmann, Michael Friedrich, Nikola D. Komerički, Laura K. Diebel, Verena Stieß, Dominique Bougeard, Yuji Yamamoto, Felix Reichmann, Marvin H. Zöllner, Claus Dahl, Lars R. Schreiber, Hendrik Bluhm
Year
2024
Paper ID
37804
Status
Preprint
Abstract Read
~2 min
Abstract Words
161
Citations
N/A
Abstract
This paper reports the compatibility of heterostructure-based spin qubit devices with industrial CMOS technology. It features Si/Si-Ge quantum dot devices fabricated using Infineon's 200 mm production line within a restricted thermal budget. The devices exhibit state-of-the-art charge sensing, charge noise and valley splitting characteristics, showing that industrial fabrication is not harming the heterostructure quality. These measured parameters are all correlated to spin qubit coherence and qubit gate fidelity. We describe the single electron device layout, design and its fabrication process using electron beam lithography. The incorporated standard 90 nm back-end of line flow for gate-layer independent contacting and wiring can be scaled up to multiple wiring layers for scalable quantum computing architectures. In addition, we present millikelvin characterization results. Our work exemplifies the potential of industrial fabrication methods to harness the inherent CMOS-compatibility of the Si/Si-Ge material system, despite being restricted to a reduced thermal budget. It paves the way for advanced quantum processor architectures with high yield and device quality.
Why This Paper Matters
- This paper contributes to the Trapped-Ion Quantum Computing research area in the Quantum Articles archive.
- It adds a 2024 reference point for readers tracking recent quantum research.
- This paper reports the compatibility of heterostructure-based spin qubit devices with industrial CMOS technology.
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