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Spin Qubits Silicon Quantum Computing Quantum Chemistry

Single Spin Logic Implementation of VLSI Adders

arXiv
Authors: Soumitra Shukla, Bahniman Ghosh

Year

2011

Paper ID

29606

Status

Preprint

Abstract Read

~2 min

Abstract Words

96

Citations

N/A

Abstract

Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.

Why This Paper Matters

  • This paper contributes to the Quantum Chemistry research area in the Quantum Articles archive.
  • It adds a 2011 reference point for readers tracking recent quantum research.
  • Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm.

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References & Citation Signals

[1] DOI https://doi.org/arXiv:1111.5086 [2] arXiv https://arxiv.org/abs/1111.5086 [3] Publisher https://arxiv.org/abs/1111.5086

Local Citation Graph (Related-Paper Links)

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