Zero-Noise Extrapolation via Cyclic Permutations of Quantum Circuit Layouts

Increasing the utility of currently available Noisy Intermediate-Scale Quantum (NISQ) devices requires developing efficient methods to mitigate hardware errors, taking into account the constraints of these devices such as medium number of qubits and limited connectivity between them. In this work we propose a novel Cyclic Layout Permutations based Zero Noise Extrapolation (CLP-ZNE) protocol for such a task. The method leverages the inherent non-uniformity of gate errors in NISQ hardware and exploits symmetries of quantum circuits with one-dimensional connectivity to extrapolate the expectation value, averaged over cyclic circuit layout permutations, to the level of zero noise. In contrast to the previous layout permutation based approaches, for n qubit circuit CLP-ZNE requires measurements of only O(n) different circuit layouts to reconstruct the noiseless expected value. When benchmarked against noise channels modeling the IBM Torino quantum computer, the method reduces a typical expectation value error by an order of magnitude, depending on the protocol specifications. By employing a noise model derived from real hardware specifications, including both depolarizing and T₁/T₂ relaxation processes, these results give evidence for the applicability of CLP-ZNE to present-day NISQ processors.