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Quantum Circuit Design Gate Engineering Quantum Error Correction Fault Tolerance

Circuit Depth Reduction for Gate-Model Quantum Computers.

Europe PMC
Authors: Gyongyosi L, Imre S.

Year

2020

Paper ID

34438

Status

Peer-reviewed

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~2 min

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0

Citations

60

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[1] DOI https://doi.org/10.1038/s41598-020-67014-5 [2] Publisher https://europepmc.org/article/MED/32641766

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Current Paper #34438 #59444 Qubit-oscillator concatenated c...

External citation index: OpenAlex citation signal • updated 2026-05-05 23:33:30

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