Fault Tolerant Synthesis of Reversible Circuits

Reversible computing has emerged as a possible low cost alternative to conventional computing in terms of speed, power consumption and computing capability. In order to achieve reliable circuits in reversible computing, provision for fault tolerance is necessary. A number of fault models, fault tolerant techniques (such as parity-preserving) and testing approaches have proposed in literature. This dissertation exploits parity-preserving characteristics of two reversible gates which provide low cost parity-preserving based fault tolerance. In order to extend online testability of reversible circuits, the substitution of Peres gate has been presented. The online testing capabilities of MCF including Swap and Fredkin gates were also identifies. Finally a tool was developed to implement all above substitutions and converting any reversible circuit to parity-preserving based fault tolerant circuit.