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Paper 1

Correcting biased noise using Gottesman-Kitaev-Preskill repetition code with noisy ancilla

Zhifei Li, Daiqin Su

Year

2023

Journal

arXiv preprint

DOI

arXiv:2308.01549

arXiv

2308.01549

Concatenation of a bosonic code with a qubit code is one of the promising ways to achieve fault-tolerant quantum computation. As one of the most important bosonic codes, Gottesman-Kitaev-Preskill (GKP) code is proposed to correct small displacement error in phase space. If the noise in phase space is biased, square-lattice GKP code can be concatenated with XZZX surface code or repetition code that promises a high fault-tolerant threshold to suppress the logical error. In this work, we study the performance of GKP repetition codes with physical ancillary GKP qubits in correcting biased noise. We find that there exists a critical value of noise variance for the ancillary GKP qubit such that the logical Pauli error rate decreases when increasing the code size. Furthermore, one round of GKP error correction has to be performed before concatenating with repetition code. Our study paves the way for practical implementation of error correction by concatenating GKP code with low-level qubit codes.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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