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Paper 1

Constructions and performance of hyperbolic and semi-hyperbolic Floquet codes

Oscar Higgott, Nikolas P. Breuckmann

Year

2023

Journal

arXiv preprint

DOI

arXiv:2308.03750

arXiv

2308.03750

We construct families of Floquet codes derived from colour code tilings of closed hyperbolic surfaces. These codes have weight-two check operators, a finite encoding rate and can be decoded efficiently with minimum-weight perfect matching. We also construct semi-hyperbolic Floquet codes, which have improved distance scaling, and are obtained via a fine-graining procedure. Using a circuit-based noise model that assumes direct two-qubit measurements, we show that semi-hyperbolic Floquet codes can be $48\times$ more efficient than planar honeycomb codes and therefore over $100\times$ more efficient than alternative compilations of the surface code to two-qubit measurements, even at physical error rates of $0.3\%$ to $1\%$. We further demonstrate that semi-hyperbolic Floquet codes can have a teraquop footprint of only 32 physical qubits per logical qubit at a noise strength of $0.1\%$. For standard circuit-level depolarising noise at $p=0.1\%$, we find a $30\times$ improvement over planar honeycomb codes and a $5.6\times$ improvement over surface codes. Finally, we analyse small instances that are amenable to near-term experiments, including a Floquet code derived from the Bolza surface that encodes four logical qubits into 16 physical qubits.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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