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Paper 1

A complete continuous-variable quantum computation architecture based on the 2D spatiotemporal cluster state

Peilin Du, Jing Zhang, Tiancai Zhang, Rongguo Yang, Jiangrui Gao

Year

2023

Journal

arXiv preprint

DOI

arXiv:2312.13877

arXiv

2312.13877

Continuous-variable measurement-based quantum computation, which requires deterministically generated large-scale cluster state, is a promising candidate for practical, scalable, universal, and fault-tolerant quantum computation. In this work, based on our compact and scalable scheme of generating a two-dimensional spatiotemporal cluster state, a complete architecture including cluster state preparation, gate implementations, and error correction, is proposed. First, a scheme for generating two-dimensional large-scale continuous-variable cluster state by multiplexing both the temporal and spatial domains is proposed. Then, the corresponding gate implementations by gate teleportation are discussed and the actual gate noise from the generated cluster state is considered. After that, the quantum error correction can be further achieved by utilizing the square-lattice Gottesman-Kitaev-Preskill (GKP) code. Finally, a fault-tolerant quantum computation can be realized by introducing bias into the square-lattice GKP code (to protect against phase-flip errors) and concatenating a repetition code (to handle the residual bit-flip errors), with a squeezing threshold of 12.3 dB. Our work provides a possible option for a complete fault-tolerant quantum computation architecture in the future.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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