Compare Papers

Paper 1

Qudit surface codes and hypermap codes

Zihan Lei

Year

2021

Journal

arXiv preprint

DOI

arXiv:2112.01752

arXiv

2112.01752

In this article, we define homological quantum codes in arbitrary qudit dimensions $D\geq 2$ by directly defining CSS operators on a 2-Complex $Σ$. If the 2-Complex is constructed from a surface, we obtain a qudit surface code. We then prove that the dimension of the code we define always equals the size of the first homology group of $Σ$. We also define the distance of the codes in this setting, finding that they share similar properties with their qubit counterpart. Additionally, we generalize the hypermap-homology quantum code proposed by Martin Leslie to the qudit case. For every such hypermap code, we construct an abstract 2-Complex whose homological quantum code is equivalent to the hypermap code.

Open paper

Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

Open paper