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Paper 1

New Binary Quantum Codes Constructed from Quasi-Cyclic Codes

Chaofeng Guan, Ruihu Li, Liangdong Lu, Yu Yao

Year

2021

Journal

arXiv preprint

DOI

arXiv:2112.07137

arXiv

2112.07137

It is well known that quantum codes can be constructed by means of classical symplectic dual-containing codes. This paper considers a family of two-generator quasi-cyclic codes and derives sufficient conditions for these codes to be symplectic dual-containing. Then, a new method for constructing binary quantum codes using symplectic dual-containing codes is proposed. As an application, we construct 8 binary quantum codes that exceed the best-known results. Further, another 36 new binary quantum codes are obtained by propagation rules, all of which improve the lower bound on the minimum distances.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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