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Paper 1

Nonadiabatic holonomic multiqubit controlled gates

P. Z. Zhao, G. F. Xu, D. M. Tong

Year

2019

Journal

arXiv preprint

DOI

arXiv:1912.09796

arXiv

1912.09796

Previous schemes of nonadiabatic holonomic quantum computation were focused mainly on realizing a universal set of elementary gates. Multiqubit controlled gates could be built by decomposing them into a series of the universal gates. In this article, we propose an approach for realizing nonadiabatic holonomic multiqubit controlled gates in which a $(n+1)$-qubit controlled-$(\boldsymbol{\mathrm{n}\cdot \mathrmσ})$ gate is realized by $(2n-1)$ basic operations instead of decomposing it into the universal gates, whereas an $(n+1)$-qubit controlled arbitrary rotation gate can be obtained by combining only two such controlled-$(\boldsymbol{\mathrm{n}\cdot \mathrmσ})$ gates. Our scheme greatly reduces the operations of nonadiabatic holonomic quantum computation.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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