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Paper 1
An Optimized Nearest Neighbor Compliant Quantum Circuit for 5-qubit Code
Arijit Mondal, Keshab K. Parhi
- Year
- 2024
- Journal
- arXiv preprint
- DOI
- arXiv:2410.06375
- arXiv
- 2410.06375
The five-qubit quantum error correcting code encodes one logical qubit to five physical qubits, and protects the code from a single error. It was one of the first quantum codes to be invented, and various encoding circuits have been proposed for it. In this paper, we propose a systematic procedure for optimization of encoder circuits for stabilizer codes. We start with the systematic construction of an encoder for a five-qubit code, and optimize the circuit in terms of the number of quantum gates. Our method is also applicable to larger stabilizer codes. We further propose nearest neighbor compliant (NNC) circuits for the proposed encoder using a single swap gate, as compared to three swap gates in a prior design.
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A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI
Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero
- Year
- 2026
- Journal
- arXiv preprint
- DOI
- arXiv:2605.01035
- arXiv
- 2605.01035
In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.
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