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Paper 1

Measurement-free, scalable and fault-tolerant universal quantum computing

Friederike Butt, David F. Locher, Katharina Brechtelsbauer, Hans Peter Büchler, Markus Müller

Year

2024

Journal

arXiv preprint

DOI

arXiv:2410.13568

arXiv

2410.13568

Reliable execution of large-scale quantum algorithms requires robust underlying operations and this challenge is addressed by quantum error correction (QEC). Most modern QEC protocols rely on measurements and feed-forward operations, which are experimentally demanding, and often slow and prone to high error rates. Additionally, no single error-correcting code intrinsically supports the full set of logical operations required for universal quantum computing, resulting in an increased operational overhead. In this work, we present a complete toolbox for fault-tolerant universal quantum computing without the need for measurements during algorithm execution by combining the strategies of code switching and concatenation. To this end, we develop new fault-tolerant, measurement-free protocols to transfer encoded information between 2D and 3D color codes, which offer complementary and in combination universal sets of robust logical gates. We identify experimentally realistic regimes where these protocols surpass state-of-the-art measurement-based approaches. Moreover, we extend the scheme to higher-distance codes by concatenating the 2D color code with itself and by integrating code switching for operations that lack a natively fault-tolerant implementation. Our measurement-free approach thereby provides a practical and scalable pathway for universal quantum computing on state-of-the-art quantum processors.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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