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Paper 1

LUCI in the Surface Code with Dropouts

Dripto M. Debroy, Matt McEwen, Craig Gidney, Noah Shutty, Adam Zalcman

Year

2024

Journal

arXiv preprint

DOI

arXiv:2410.14891

arXiv

2410.14891

Recently, usage of detecting regions facilitated the discovery of new circuits for fault-tolerantly implementing the surface code. Building on these ideas, we present LUCI, a framework for constructing fault-tolerant circuits flexible enough to construct aperiodic and anisotropic circuits, making it a clear step towards quantum error correction beyond static codes. We show that LUCI can be used to adapt surface code circuits to lattices with imperfect qubit and coupler yield, a key challenge for fault-tolerant quantum computers using solid-state architectures. These circuits preserve spacelike distance for isolated broken couplers or isolated broken measure qubits in exchange for halving timelike distance, substantially reducing the penalty for dropout compared to the state of the art and creating opportunities in device architecture design. For qubit and coupler dropout rates of 1% and a patch diameter of 15, LUCI achieves an average spacelike distance of 13.1, compared to 9.1 for the best method in the literature. For a SI1000(0.001) circuit noise model, this translates to a 36x improvement in median logical error rate per round, a factor which increases with device performance. At these dropout and error rates, LUCI requires roughly 25% fewer physical qubits to reach algorithmically relevant one-in-a-trillion logical codeblock error rates.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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