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Paper 1

Floquetifying stabiliser codes with distance-preserving rewrites

Benjamin Rodatz, Boldizsár Poór, Aleks Kissinger

Year

2024

Journal

arXiv preprint

DOI

arXiv:2410.17240

arXiv

2410.17240

Stabiliser codes with large weight measurements can be challenging to implement fault-tolerantly. To overcome this, we propose a Floquetification procedure which, given a stabiliser code, synthesises a novel Floquet code that only uses single- and two-qubit operations. Moreover, this procedure preserves the distance and number of logicals of the original code. The new Floquet code requires additional physical qubits. This overhead is linear in the weight of the largest measurement of the original code. Our method is based on the ZX calculus, a graphical language for representing and rewriting quantum circuits. However, a problem arises with the use of ZX in the context of rewriting error-correcting codes: ZX rewrites generally do not preserve code distance. Tackling this issue, we define the notion of distance-preserving rewrite that enables the transformation of error-correcting codes without changing their distance. These distance-preserving rewrites are used to decompose arbitrary weight stabiliser measurements into quantum circuits with single- and two-qubit operations. As we only use distance-preserving rewrites, we are guaranteed that a single error in the resulting circuit creates at most a single error on the data qubits. These decompositions enable us to generalise the Floquetification procedure of [arXiv:2307.11136] to arbitrary stabiliser codes, provably preserving the distance and number of logicals of the original code.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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