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Paper 1
Computation with quantum Reed-Muller codes and their mapping onto 2D atom arrays
Anqi Gong, Joseph M. Renes
- Year
- 2024
- Journal
- arXiv preprint
- DOI
- arXiv:2410.23263
- arXiv
- 2410.23263
We give a fault tolerant construction for error correction and computation using two punctured quantum Reed-Muller (PQRM) codes. In particular, we consider the $[[127,1,15]]$ self-dual doubly-even code that has transversal Clifford gates (CNOT, H, S) and the triply-even $[[127,1,7]]$ code that has transversal T and CNOT gates. We show that code switching between these codes can be accomplished using Steane error correction. For fault-tolerant ancilla preparation we utilize the low-depth hypercube encoding circuit along with different code automorphism permutations in different ancilla blocks, while decoding is handled by the high-performance classical successive cancellation list decoder. In this way, every logical operation in this universal gate set is amenable to extended rectangle analysis. The CNOT exRec has a failure rate approaching $10^{-9}$ at $10^{-3}$ circuit-level depolarizing noise. Furthermore, we map the PQRM codes to a 2D layout suitable for implementation in arrays of trapped atoms and try to reduce the circuit depth of parallel atom movements in state preparation. The resulting protocol is strictly fault-tolerant for the $[[127,1,7]]$ code and practically fault-tolerant for the $[[127,1,15]]$ code. Moreover, each patch requires a permutation consisting of $7$ sub-hypercube swaps only. These are swaps of rectangular grids in our 2D hypercube layout and can be naturally created with acousto-optic deflectors (AODs). Lastly, we show for the family of $[[2^{2r},{2r\choose r},2^r]]$ QRM codes that the entire logical Clifford group can be achieved using only permutations, transversal gates, and fold-transversal gates.
Open paperPaper 2
A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI
Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero
- Year
- 2026
- Journal
- arXiv preprint
- DOI
- arXiv:2605.01035
- arXiv
- 2605.01035
In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.
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