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Paper 1

Detrimental non-Markovian errors for surface code memory

John F Kam, Spiro Gicev, Kavan Modi, Angus Southwell, Muhammad Usman

Year

2024

Journal

arXiv preprint

DOI

arXiv:2410.23779

arXiv

2410.23779

The realization of fault-tolerant quantum computers hinges on effective quantum error correction protocols, whose performance significantly relies on the nature of the underlying noise. In this work, we directly study the structure of non-Markovian correlated errors and their impact on surface code memory performance. Specifically, we compare surface code performance under non-Markovian noise and independent circuit-level noise, while keeping marginal error rates constant. Our analysis shows that while not all temporally correlated structures are detrimental, certain structures, particularly multi-time "streaky" correlations affecting syndrome qubits and two-qubit gates, can severely degrade logical error rate scaling. Furthermore, we discuss our results in the context of recent quantum error correction experiments on physical devices. These findings underscore the importance of understanding and mitigating non-Markovian noise toward achieving practical, fault-tolerant quantum computing.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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