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Paper 1

An Efficient Error Estimation Method in Quantum Key Distribution

Yingjian Wang, Yilun Hai, Buniechukwu Njoku, Koteswararao Kondepu, Riccardo Bassoli, Frank H. P. Fitzek

Year

2024

Journal

arXiv preprint

DOI

arXiv:2411.07160

arXiv

2411.07160

Error estimation is an important step for error correction in quantum key distribution. Traditional error estimation methods require sacrificing a part of the sifted key, forcing a trade-off between the accuracy of error estimation and the size of the partial sifted key to be used and discarded. In this paper, we propose a hybrid approach that aims to preserve the entire sifted key after error estimation while preventing Eve from gaining any advantage. The entire sifted key, modified and extended by our proposed method, is sent for error estimation in a public channel. Although accessible to an eavesdropper, the modified and extended sifted key ensures that the number of attempts to crack it remains the same as when no information is leaked. The entire sifted key is preserved for subsequent procedures, indicating the efficient utilization of quantum resources.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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