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Paper 1

Correction of circuit faults in a stacked quantum memory using rank-metric codes

Nicolas Delfosse, Gilles Zémor

Year

2024

Journal

arXiv preprint

DOI

arXiv:2411.09173

arXiv

2411.09173

We introduce a model for a stacked quantum memory made with multi-qubit cells, inspired by multi-level flash cells in classical solid-state drive, and we design quantum error correction codes for this model by generalizing rank-metric codes to the quantum setting. Rank-metric codes are used to correct faulty links in classical communication networks. We propose a quantum generalization of Gabidulin codes, which is one of the most popular family of rank-metric codes, and we design a protocol to correct faults in Clifford circuits applied to a stacked quantum memory based on these codes. We envision potential applications to the optimization of stabilizer states and magic states factories, and to variational quantum algorithms. Further work is needed to make this protocol practical. It requires a hardware platform capable of hosting multi-qubit cells with low crosstalk between cells, a fault-tolerant syndrome extraction circuit for rank-metric codes and an associated efficient decoder.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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