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Paper 1
All-optical cat-code quantum error correction
Jacob Hastrup, Ulrik Lund Andersen
- Year
- 2022
- Journal
- Physical Review Research
- DOI
- 10.1103/PhysRevResearch.4.043065
- arXiv
- -
The cat code is a promising encoding scheme for bosonic quantum error correction as it allows for correction against losses—the dominant error mechanism in most bosonic systems. However, it has remained unclear how the required syndrome measurement and recovery can be implemented in the optical regime. Here, we introduce a teleportation-based error-correction scheme for the cat code, using elements suitable for an optical setting. The scheme detects and corrects single-photon losses while restoring the amplitude of the cat states, thereby greatly suppressing the accumulation of errors in lossy channels.
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A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI
Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero
- Year
- 2026
- Journal
- arXiv preprint
- DOI
- arXiv:2605.01035
- arXiv
- 2605.01035
In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.
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