Compare Papers
Paper 1
A family of [[6k, 2k, 2]] codes for practical, scalable adiabatic quantum computation
Anand Ganti, Uzoma Onunkwo, Kevin Young
- Year
- 2013
- Journal
- arXiv preprint
- DOI
- arXiv:1309.1674
- arXiv
- 1309.1674
In this work, we introduce a new family of [[6k, 2k, 2]] codes designed specifically to be compatible with adiabatic quantum computation. These codes support computationally universal sets of weight-two logical operators and are particularly well-suited for implementing dynamical decoupling error suppression. For Hamiltonians embeddable on a planar graph of fixed degree, our encoding maintains a planar connectivity graph and increase the graph degree by only two. These codes are the first known to possess these features.
Open paperPaper 2
A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI
Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero
- Year
- 2026
- Journal
- arXiv preprint
- DOI
- arXiv:2605.01035
- arXiv
- 2605.01035
In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.
Open paper