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Paper 1
Fibre bundle framework for unitary quantum fault tolerance
Daniel Gottesman, Lucy Liuxuan Zhang
- Year
- 2013
- Journal
- arXiv preprint
- DOI
- arXiv:1309.7062
- arXiv
- 1309.7062
We introduce a differential geometric framework for describing families of quantum error-correcting codes and for understanding quantum fault tolerance. This work unifies the notion of topological fault tolerance with fault tolerance in other kinds of quantum error-correcting codes. In particular, we use fibre bundles with a natural flat projective connection to study the transformation of codewords under unitary fault-tolerant evolutions. We show that the fault-tolerant logical operations are given by the monodromy group for either of two bundles, both of which have flat projective connections. As concrete realizations of the general framework, we construct the bundles explicitly for two examples of fault-tolerant families of operations, the qudit transversal gates and the string operators in the toric code.
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A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI
Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero
- Year
- 2026
- Journal
- arXiv preprint
- DOI
- arXiv:2605.01035
- arXiv
- 2605.01035
In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.
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