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Paper 1

Characterizing Universal Gate Sets via Dihedral Benchmarking

Arnaud Carignan-Dugas, Joel J. Wallman, Joseph Emerson

Year
2015
Journal
arXiv preprint
DOI
arXiv:1508.06312
arXiv
1508.06312

We describe a practical experimental protocol for robustly characterizing the error rates of non-Clifford gates associated with dihedral groups, including gates in SU(2) associated with arbitrarily small angle rotations. Our dihedral benchmarking protocol is a generalization of randomized benchmarking that relaxes the usual unitary 2-design condition. Combining this protocol with existing randomized benchmarking schemes enables an efficient means of characterizing universal gate sets for quantum information processing in a way that is independent of state-preparation and measurement errors. In particular, our protocol enables direct benchmarking of the $T$ gate (sometime called $π/8$-gate) even for the gate-dependent error model that is expected in leading approaches to fault-tolerant quantum computation.

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Paper 2

Building a spin quantum bit register using semiconductor nanowires.

Baugh J, Fung JS, Mracek J, LaPierre RR.

Year
2010
Journal
Nanotechnology
DOI
10.1088/0957-4484/21/13/134018
arXiv
-

No abstract.

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