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Paper 1

Parallel decoding of multiple logical qubits in tensor-network codes

Terry Farrelly, Robert J. Harris, Nathan A. McMahon, Thomas M. Stace

Year

2020

Journal

arXiv preprint

DOI

arXiv:2012.07317

arXiv

2012.07317

We consider tensor-network stabilizer codes and show that their tensor-network decoder has the property that independent logical qubits can be decoded in parallel. As long as the error rate is below threshold, we show that this parallel decoder is essentially optimal. As an application, we verify this for the max-rate holographic Steane (heptagon) code. For holographic codes this tensor-network decoder was shown to be efficient with complexity polynomial in n, the number of physical qubits. Here we show that, by using the parallel decoding scheme, the complexity is also linear in k, the number of logical qubits. Because the tensor-network contraction is computationally efficient, this allows us to exactly contract tensor networks corresponding to codes with up to half a million qubits. Finally, we calculate the bulk threshold (the threshold for logical qubits a fixed distance from the code centre) under depolarizing noise for the max-rate holographic Steane code to be 9.4%.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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