Compare Papers
Paper 1
Addressable fault-tolerant universal quantum gate operations for high-rate lift-connected surface codes
Josias Old, Juval Bechar, Markus Müller, Sascha Heußen
- Year
- 2025
- Journal
- arXiv preprint
- DOI
- arXiv:2511.10191
- arXiv
- 2511.10191
Quantum low-density parity check (qLDPC) codes are among the leading candidates to realize error-corrected quantum memories with low qubit overhead. Potentially high encoding rates and large distance relative to their block size make them appealing for practical suppression of noise in near-term quantum computers. In addition to increased qubit-connectivity requirements compared to more conventional topological quantum error correcting codes, qLDPC codes remain notoriously hard to compute with. In this work, we introduce a construction to implement all Clifford quantum gate operations on the recently introduced lift-connected surface (LCS) codes (Old et al. 2024). These codes can be implemented in a 3D-local architecture and achieve asymptotic scaling $[[n, \mathcal{O}(n^{1/3}), \mathcal{O}(n^{1/3})]]$. In particular, LCS codes realize favorable instances with small numbers of qubits: For the $[[15,3,3]]$ LCS code, we provide deterministic fault-tolerant (FT) circuits of the logical gate set $\{\overline{H}_i, \overline{H}_i, \overline{C_i X_j}\}_{i,j \in (0,1,2)}$ based on flag qubits. By adding a procedure for FT magic state preparation, we show quantitatively how to realize an FT universal gate set in $d=3$ LCS codes. Numerical simulations indicate that our gate constructions can attain pseudothresholds in the range $p_{\mathrm{th}} \approx 4.8\cdot 10^{-3}-1.2\cdot 10^{-2}$ for circuit-level noise. The schemes use a moderate number of qubits and are therefore feasible for near-term experiments, facilitating progress for fault-tolerant error corrected logic in high-rate qLPDC codes.
Open paperPaper 2
Decoder Switching: Breaking the Speed-Accuracy Tradeoff in Real-Time Quantum Error Correction
Riki Toshio, Kaito Kishi, Jun Fujisaki, Hirotaka Oshima, Shintaro Sato, Keisuke Fujii
- Year
- 2025
- Journal
- arXiv preprint
- DOI
- arXiv:2510.25222
- arXiv
- 2510.25222
The realization of fault-tolerant quantum computers hinges on the construction of high-speed, high-accuracy, real-time decoding systems. The persistent challenge lies in the fundamental trade-off between speed and accuracy: efforts to improve the decoder's accuracy often lead to unacceptable increases in decoding time and hardware complexity, while attempts to accelerate decoding result in a significant degradation in logical error rate. To overcome this challenge, we propose a novel framework, decoder switching, which balances these competing demands by combining a faster, soft-output decoder ("weak decoder") with a slower, high-accuracy decoder ("strong decoder"). In usual rounds, the weak decoder processes error syndromes and simultaneously evaluates its reliability via soft information. Only when encountering a decoding window with low reliability do we switch to the strong decoder to achieve more accurate decoding. Numerical simulations suggest that this framework can achieve accuracy comparable to, or even surpassing, that of the strong decoder, while maintaining an average decoding time on par with the weak decoder. We also develop an online decoding scheme tailored to our framework, named double window decoding, and elucidate the criteria for preventing an exponential slowdown of quantum computation. These findings break the long-standing speed-accuracy trade-off, paving the way for scalable real-time decoding devices.
Open paper