Compare Papers

Paper 1

Logical Performance of 9 Qubit Compass Codes in Ion Traps with Crosstalk Errors

Dripto M. Debroy, Muyuan Li, Shilin Huang, Kenneth R. Brown

Year

2019

Journal

arXiv preprint

DOI

arXiv:1910.08495

arXiv

1910.08495

We simulate four quantum error correcting codes under error models inspired by realistic noise sources in near-term ion trap quantum computers: $T_2$ dephasing, gate overrotation, and crosstalk. We use this data to find preferred codes for given error parameters along with logical error biases and a pseudothreshold which compares the physical and logical gate failure rates for a CNOT gate. Using these results we conclude that Bacon-Shor-13 is the most promising near term candidate as long as the impact of crosstalk can be mitigated through other means.

Open paper

Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

Open paper