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Paper 1

Memory-assisted decoder for approximate Gottesman-Kitaev-Preskill codes

Kwok Ho Wan, Alex Neville, W. S. Kolthammer

Year

2019

Journal

arXiv preprint

DOI

arXiv:1912.00829

arXiv

1912.00829

We propose a quantum error correction protocol for continuous-variable finite-energy, approximate Gottesman-Kitaev-Preskill (GKP) states undergoing small Gaussian random displacement errors, based on the scheme of Glancy and Knill [Phys. Rev. A {\bf 73}, 012325 (2006)]. We show that combining multiple rounds of error-syndrome extraction with Bayesian estimation offers enhanced protection of GKP-encoded qubits over comparible single-round approaches. Furthermore, we show that the expected total displacement error incurred in multiple rounds of error followed by syndrome extraction is bounded by $2\sqrtπ$. By recompiling the syndrome-extraction circuits, we show that all squeezing operations can be subsumed into auxiliary state preparation, reducing them to beamsplitter transformations and quadrature measurements.

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Paper 2

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel Báscones, Arshpreet Singh Maan, Valentin Savin, Francisco Garcia-Herrero

Year

2026

Journal

arXiv preprint

DOI

arXiv:2605.01035

arXiv

2605.01035

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

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